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A83516 Series
Preliminary
Document Title 8 Bit Microcontroller Revision History
Rev. No.
0.0
8 Bit Microcontroller
History
Initial issue
Issue Date
November 25, 1998
Remark
Preliminary
PRELIMINARY
(November, 1998, Version 0.0)
AMIC Technology, Inc.
A83516 Series
Preliminary
Features
n 8-bit CMOS microcontroller n Fully static design with power saving idle mode and power down mode n Low standby current at full supply voltage n Versions for 12/24/40MHZ operating frequency n On chip 256B RAM n On chip 64KB X 8 MASK-ROM program memory n 64K bytes external data memory space n Four 8-bit bidirectional ports n Three 16-bit Timers/Counters (Timer 2 with up/down counter feature) n One full duplex serial port n Boolean processor n Six interrupt sources, two priority levels n Available in 40-pin P-DIP and 44-pin PLCC packages
8 Bit Microcontroller
General Description
The AMIC A83516 is a high-performance 8-bit microcontroller. It is compatible with the industry standard 80C52 microcontroller series. The A83516 contains a 256B RAM, 64KB X 8 ROM, four 8-bit bidirectional parallel ports, three 16-bit timer/counters, a serial port and six interrupt sources with two priority levels. The A83516 has two power reduction modes, idle mode and power-down mode. It supports 64KB external data memory.
Pin Configurations
n P-DIP n PLCC
P1.1,T2EX
P0.0,AD0
P0.1,AD1 42
P0.2,AD2 41
T2,P1.0 T2EX,P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD,P3.0 TXD,P3.1 INT0,P3.2 INT1,P3.3 T0,P3.4 T1,P3.5 WR,P3.6 RD,P3.7 XTAL2 XTAL1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC P0.0,AD0 P0.1,AD1 P0.2,AD2 P0.3,AD3 P0.4,AD4 P0.5,AD5 P0.6,AD6 P0.7,AD7 EA ALE PSEN P2.7,A15 P2.6,A14 P2.5,A13 P2.4,A12 P2.3,A11 P2.2,A10 P2.1,A9 P2.0,A8
6
5
4
3
2
1
44
43
P1.5 P1.6 P1.7 RST RXD,P3.0 NC TXD,P3.1 INT0, P3.2 INT1,P3.3 T0,P3.4 T1,P3.5
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
40 39 38 37 36 35 34 33 32 31 30 29
P0.3,AD3
P1.0,T2
VCC
P1.4
P1.3
P1.2
NC
P0.4,AD4 P0.5,AD5 P0.6,AD6 P0.7,AD7 EA NC ALE PSEN P2.7,A15 P2.6,A14 P2.5,A13
XTAL1
WR,P3.6
P2.2,A10
P2.3,A11
RD,P3.7 XTAL2
GND NC
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AMIC Technology, Inc.
P2.4,A12
P2.0,A8
P2.1,A9
A83516
A83516L
A83516 Series
Block Diagram
PSEN
ALE EA
RST
XTAL1
XTAL2
P0.0-P0.7
(AD0-AD7)
P2.0-P2.7
A8-A15
64K BYTE ROM SFR
TIMING AND CONTROL
OSCILLATOR PORT 0 ADDRESS PORT 2 ADDRESS
CPU CORE
TIMER 2
INTERRUPT
SERIAL PORT
TIMER 0.1
256B RAM PORT 1 PORT 3
P1.0-P1.7
P3.0-P3.7
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AMIC Technology, Inc.
A83516 Series
Pin Description
Pin No. Symbol P-DIP 1-8 PLCC 2-9 P1.0 - P1.7 I/O I/O I 9 10 - 17 10 11, 13 - 19 I O I I I I O O 18 19 20 21 - 28 20 21 22 24 - 31 XTAL2 XTAL1 GND P2.0 - P2.7 O I I I/O RST P3.0 - P3.7 I I/O Port1. Port1 is a bidirectional I/O port with internal pull-ups. Pin P1.0 and P1.1 also provide alternate functions as follows: P1.0 P1.1 T2 T2EX Timer/Counter2 external input/clock out Timer/Counter2 capture/reload input Type Description
Reset input, active high. It must be kept high for at least two machine cycles to be recognized by the processor Port3. Port3 is a bidirectional I/O port with internal pull-ups. Port3 pins also serve alternate functions as follows: P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
RXD TXD
INT0
Serial receive port Serial transmit port External interrupt 0 External interrupt 1 Timer/Counter 0 input Timer/Counter 1 input External data memory write strobe External data memory read strobe
INT1
T0 T1
WR RD
Crystal2. This is the output of crystal oscillator. It is the inversion of XTAL1 Crystal1. This is the input of crystal oscillator. It can be driven by an external clock Ground Port2. Port2 is a bidirectional I/O port with internal pull-ups. Port2 is also the multiplexed upper-order address bus during accesses to external data memory Program Store Enable : active low. The read strobe to external program memory. PSEN is activated in each machine cycle when fetching external program memory Address Latch Enable : active high. ALE is used to enable the address latch that separates the data on Port 0 External Access Enable : active low. It is held low to enable the device to fetch code from external program memory Port0. Port0 is an open drain, bidirectional I/O port. Port0 is also the multiplexed low-order address bus during accesses to external data memory Power supply
29
32
PSEN
O
30 31 32 - 39
33 35 36 - 43
ALE
O I I/O
EA
P0.7 - P0.0
40
44
VCC
I
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(November, 1998, Version 0.0)
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AMIC Technology, Inc.
A83516 Series
Functional Description
The A83516 is a high speed 8-bit microcontroller. The architecture consists of a core controller, four general purposes I/O ports, 256 bytes RAM internal register, 64K bytes ROM and a serial port. This microcontroller supports 111 opcodes and executes instructions in 12 clock/machine cycle. It can reference both a 64K program address space and a 64K data storage space.
Timer/Counter 0, 1 and 2
Timer 0,1 and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0. TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TMOD and TCON registers support control function for Timer 0 and Timer 1. The T2CON register provides control function for Timer 2. When operating reload/capture mode, RCAP2H and RCAP2L will be used.
N/C EXTERNAL OSCILLATOR SIGNAL XTAL 2
XTAL 1
VSS
Interrupt
The A83516 provides 6 interrupt modes. These consist of 2 external interrupts, 3 internal interrupts and a serial port interrupt. The enable/disable interrupt is controlled by IE register in SFR. The priority of interrupts is controlled by IP register in SFR.
Figure 2. External Clock Drive configuration Power Reduce Mode
IDLE Mode It is executed by IDLE bit of PCON register in SFR. In idle mode, the clock to microcontroller core is stopped. The status in microcontroller core and I/O data are kept. The microcontroller will stop idle status when either a reset or an interrupt occurs. POWER-DOWN Mode It is executed by PD bit of PCON register in SFR. In power-down mode, the oscillator clock will stop. The data in RAM and status in SFR will be kept. The only way to exit power-down mode is to reset this chip. RESET The external reset signal must be held high for at least two machine cycles during the oscillator running. After reset, the ports are held high, SP register to 07H, all of the other SFR registers except SBUF to 00H, and SBUF is not reset.
Serial Port Transfer
The A83516 provides a full duplex serial transfer function. This function is controlled by SCON register in SFR. And the data is storaged in SBUF register during transmitting and receiving.
Oscillator Characteristics
The oscillator connections are shown as Figure 1. And Figure 2. When quartz crystal is used, C1 and C2 are 30pF shown in Figure 1. When external clock is used, the internal clock will be gotten through a divide-by-two flip-flop. When starting up, the input loading for XTAL1 pin is 100pF. This is due to interaction between the amplifier and its feedback capacitance interaction. After the external signal meets the VIL and VIH specification the capacitance will not exceed 20pF.
C2 XTAL 2 C1 XTAL 1 VSS
C1,C2 = 30pF 10pF for Crystals Figure 1. Oscillator Connections
PRELIMINARY
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AMIC Technology, Inc.
A83516 Series
Recommended DC Operating Conditions (TA = -25 to + 85 C C)
Symbol VCC GND VIH* VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.4 0 Typ. 5.0 0 Max. 5.5 0 VCC+0.2 0.8 Unit V V V V
* XTAL1 is a CMOS input. RESET is a Schmit trigger input. The min. of VIH is 3.5 Volts for these two pins.
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature, Topr . . . . . . . -25 to + 85 C C Storage Temperature, Tstg . . . . . . . . . -55 to + 125 C C 1* Power Dissipation , Pr . . . . . . . . . . . . . . . . . . . . . . 1W Soldering Temperature & Time . . . . . . . . . 260 10sec C, 1* : Operating frequency is 40MHZ
*Comments
Stresses above those listed under " Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (TA = -25 to + 85 VCC = 5V 10%) C C,
Symbol ILI
1
Parameter Input Leakage Current Output Leakage Current Operating Current
Min. -
Max. 10 10 50
Unit A A mA
Conditions VIN = GND to VCC VI/O = GND to VCC foper = 40MHZ External oscillator is on XTAL1 pin No load foper = 40MHZ VRST = GND, V EA = GND VPORT0 = VCC No crystal oscillator input VRST = GND, V EA = GND VPORT0 = VCC IOL = 2mA IOL = 4mA IOH = -100A IOH = -400A 1MHZ , 25 C
ILO ICC
IIDLE
IDLE Mode Current
-
6
mA
IPD
POWER-DOWN Mode Current Output Low Voltage (PORT1, PORT2 and PORT3) Output Low Voltage (ALE, PSEN and PORT0) Output High Voltage (PORT1, PORT2 and PORT3) Output High Voltage (ALE, PSEN and PORT0)
-
20
A V V V V pF
VOL1 VOL2 VOH1 VOH2 C1
2.4 2.4 -
0.45 0.45 10
Input Pin Capacitance
1. For RESET pin, the ILI max. is 300 A, since it has an internal pull-low of approx. 30K resistor.
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(November, 1998, Version 0.0)
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AMIC Technology, Inc.
A83516 Series
AC Characteristics (TA = -25 to + 85 VCC = 5V 10%) C C,
Symbol Program Memory Cycle tAP tALS tALH top tAO tOI
2
Parameter
Min.
Max.
Unit
ALE Pulse Width Address Valid to ALE Low Address Hold from ALE Low
2tck - 201 1tck 1tck 3tck - 20 1tck 1
2tck 1tck 1tck
ns ns ns ns ns ns ns ns
PSEN Pulse Width
ALE Low to PSEN Low
PSEN Low to Valid Instruction in
Input Instruction Hold after PSEN High Input Instruction Float after PSEN High
tIDO tIFO External Clock fOPER tCK
3 4
Clock Frequency Clock Period Clock High Time Clock Low Time
0 25 10 10
40 -
MHZ ns ns ns
tCKH tCKL
4
Data Memory Cycle tPR tPD tDHR tDFR tAR tWP tDS tDHW tAW Serial Port Cycle tSCK tKI tIKH tOKS tOKH 1. 2. 3. 4. Serial Port Clock Clock Rising Edge to Valid Input Data Input Data to Serial Clock Rising Clock Hold Time Output Data to Serial Clock Rising Edge Setup Time Output Data to Serial Clock Rising Edge Hold Time 12tck 0 11tck 1tck 11tck ns ns ns ns ns
RD Pulse Width RD Low to Valid Data in
Data Hold from RD High Data Float from RD High ALE Low to RD Low
6tck - 201 0 0 3tck 6tck - 20 1tck 1tck 3tck
1
4tck 2tck 2tck 3tck + 20 3tck + 20
1 1
ns ns ns ns ns ns ns ns ns
WR Pulse Width
Valid Data to WR Low Data Hold from WR High ALE Low to WR Low
This 20 ns is due to buffer driving delay and wire loading. Instruction cycle time is 12 tck. tck = 1/ foper There are no duty cycle requirements on the XTAL1 input.
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AMIC Technology, Inc.
A83516 Series
Timing Waveforms Program Memory Cycle
S1
S2
S3
S4
S5
S6
S1
XTAL 1
tAP
ALE
tAO
PSEN
tOP tALS
PORT 2
tALH
A8 - A15
tOI tIHO tIFO
A8 - A15
PORT 0
A0 - A7 INSTRUCTION IN
A0 - A7 INSTRUCTION IN
Clock Input Waveform
XTAL 1
tCKH tCKL tCK
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AMIC Technology, Inc.
A83516 Series
Timing Waveforms (continued) Data Memory Read Cycle
S4 XTAL 1 ALE PSEN PORT 2 PORT 0 RD tRP A0-A7 A8-A15 DATA IN tDHR tDFR A0-A7 S5 S6 S1 S2 S3 S4 S5 S6
tAR
tRD
Data Memory Write Cycle
S4 XTAL 1 ALE PSEN PORT 2 PORT 0 WR tAW tWP A0-A7 tDS A8-A15 DATA OUT tDHW S5 S6 S1 S2 S3 S4 S5 S6
Serial Port Timing - Shift Register Mode
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tSCK
CLOCK
tOKS tOKH 1 tKI tIKH
SET TI VALID VALID VALID VALID VALID VALID VALID
OUTPUT DATA
0
2
3
4
5
6
7
INPUT DATA
VALID
SET RI
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(November, 1998, Version 0.0)
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AMIC Technology, Inc.
A83516 Series
Ordering Information
Part No. A83516-12 A83516L-12 A83516-24 A83516L-24 A83516-40 A83516L-40 RAM 256 Byte 256 Byte 256 Byte 256 Byte 256 Byte 256 Byte ROM 64K Byte 64K Byte 64K Byte 64K Byte 64K Byte 64K Byte FREQ (MHZ) 12 12 24 24 40 40 Package 40L P-DIP 44L PLCC 40L P-DIP 44L PLCC 40L P-DIP 44L PLCC
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(November, 1998, Version 0.0)
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AMIC Technology, Inc.
A83516 Series
Package Information
P-DIP 40L Outline Dimensions unit: inches/mm
D 40 21
E1
1
20 E C
A2
A
A1
Base Plane
Seating Plane B B1 e1 0/15 eA
L
Symbol
A A1 A2 B B1 C D E E1 e1 L eA
Dimensions in inches Min 0.015 0.150 Nom 0.155 0.018 TYP 0.050 TYP 2.049 0.590 0.542 0.010 2.054 0.600 0.547 0.100 TYP 0.120 0.622 0.130 0.642 0.140 0.662 2.059 0.610 0.552 Max 0.210 0.160
Dimensions in mm Min 0.381 3.810 Nom 3.937 0.457 TYP 1.270 TYP 52.045 14.986 13.767 0.254 52.172 15.240 13.894 2.540 TYP 3.048 15.799 3.302 16.307 3.556 16.815 52.299 15.494 14.021 Max 5.344 4.064
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins.
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AMIC Technology, Inc.
A83516 Series
Package Information PLCC 44L Outline Dimension
unit: inches/mm
HD D 6 1 44 40 39 0.630/0.590
7
17 18 28
29
HE
E
0.014/0.0008 C
0.150 REF
L
A2
e
0.050 REF Seating Plane GD 0.630/0.590
b 0.022/0.016 b1 0.032/0.026
A1 D 0.020 MIN
A
0.004
y
Dimensions in inches Symbol A D E HD HE L Min 0.648 0.648 0.680 0.680 0.090 0 Nom 0.653 0.653 0.690 0.690 0.100 Max 0.185 0.658 0.658 0.700 0.700 0.110 10
Dimensions in mm Min 16.46 16.46 17.27 17.27 2.29 0 Nom 16.59 16.59 17.53 17.53 2.54 Max 4.70 16.71 16.71 17.78 17.78 2.79 10
Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only.
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(November, 1998, Version 0.0)
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GE
AMIC Technology, Inc.

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